Difference between revisions of "CPUProject"

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CPU project is one of the projects designed in department of computer engineering at TTU as a lab project. The main aims of this project are:
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CPU project is one of the projects designed in department of computer engineering at TTU as a lab project to provide students with some tools for studying CPU architecture.
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* Developing a simple generic CPU
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* Developing peripherals for it 
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* Writing a compiler and assembler for it
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* Compiling GCC for this architecture
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* Booting a lightweight linux on it
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This project has many interesting points and which can be used for laboratories in different courses.  
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=Hardware Design=
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= CPU implementations =
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== CPU Design==
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Currently, there are two different CPU implementations:
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[[File:BlockDiagram.png|400px|thumb|right|alt= text| Fig 1: System Block Diagram]]
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* [[picoCPU]]: a very simple, simulation oriented CPU written in VHDL.
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[[File:System_Diagram.png|400px|thumb|right|alt= text| Fig 2: System Architecture]]
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* A [[More Advanced CPU]]: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.
  
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=== Functionality Requirements ===
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= picoAssembler =
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The CPU is supposed to be able to perform the following operations:
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PicoAssembler is a simple, reconfigurable assembler that can be used together with the processors described above
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* Addition/Subtraction
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More info on this can be found on the [[PicoAssembler user manual and syntax reference]] page.
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* Increment/Decrement
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* Arithmetic and Logical Shift and Rotate through carry
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* Bitwise AND, OR, XOR and NOT
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* Negation
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* Load/Store
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* Unconditional Branch (jump)
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* Branch if zero / Branch if Overflow / Branch if Carry/ Branch if Equal
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* Clear Registers/Flags
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* PUSH / POP
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* NOP/HALT
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It can use these operations to build more sophisticated operations later.
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=== Architecture ===
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The architecture of this CPU is based on Harvard architecture which has separate instruction and data memory. The instructions are assumed to be in the instruction memory before boot.
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====Instruction Format====
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Our CPU's instruction has 8 bit of Op-code and one operand that can be as long as 32 bit.
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First 2 bits of OP-code are at the moment reserved.
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[[File:instructionformat.png|400px|thumb|right |alt= text| Fig 3: Instruction format]]
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=== Addressing Modes ===
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The following Addressing modes are supported in out processor:
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* '''direct''': program counter jumps to an address directly provided to it through instruction's operand
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* '''relative''': the program counter will jump to a location relative to its current location
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* '''indirect''': program counter will jump to an address stored in a memory location
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* '''register''': program counter will jump to an address stored in a register
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* '''indexed''': program counter will jump to an address stored in the memory with address stored in a register
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=== Instruction Set (IS)===
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The following instructions designed for the CPU:
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{| class="wikitable"
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|+ Table 1: Instruction Set
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|-
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! !! Instruction !! Register Transfer Language !! OpCode !!Reg_in_sel !!Reg_out_sel !! DPU Command !! Data To DPU !! rd_MemAddress !!  Next PC
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|-
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| 1 ||Add_A_R || A <-- A + R(operand)          || 00 0000 || ---- ||operand(2 downto 0) || 00 000 0000 10 || ----    || ----    || PC_out+1 
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|-
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| 2|| Add_A_Mem || A <-- A + Mem[Operand]      || 00 0001 || ---- || ----              || 00 000 0000 00 || ----    || Operand || PC_out+1 
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|-
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| 3|| Add_A_Dir || A <-- A + Operand            || 00 0010 || ---- || ----              || 00 000 0000 01 || Operand || ----    || PC_out+1 
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|-
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| 4|| Sub_A_R || A <-- A - R(operand)          || 00 0011 || ---- ||operand(2 downto 0) || 00 000 0001 10 || ----    || ----    || PC_out+1
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|-
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| 5|| Sub_A_Mem || A <-- A - Mem[Operand]      || 00 0100 || ---- || ----              || 00 000 0001 00 || ----    || Operand || PC_out+1 
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|-
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| 6|| Sub_A_Dir || A <-- A - Operand            || 00 0101 || ---- || ----              || 00 000 0001 01 || Operand || ---- || PC_out+1 
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|-
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| 7|| IncA || A <-- A + 1                      || 00 0110 || ---- || ----              || 00 000 0000 11 || ----    || ---- || PC_out+1 
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|-
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| 8|| DecA || A <-- A - 1                      || 00 0111 || ---- || ----              || 00 000 0001 11 || ----    || ---- || PC_out+1
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|-
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| 9|| ShiftArithR || A <-- A(7) & A(7 downto 1) || 00 1000 || ---- || ----              || 00 000 0111 00 || ----    || ---- || PC_out+1   
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|-
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| 10|| ShiftArithL || A <-- A(7) & A(5 downto 0)& '0' || 00 1001 ||---- ||---- || 00 000 1000 00 || ---- || ---- || PC_out+1   
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|-
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| 11|| ShiftA_R || A <-- A(6 downto 0)& '0'    || 00 1010 ||---- ||---- || 00 000 1010 00 || ---- || ---- || PC_out+1   
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|-
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| 12|| ShiftA_L || A <-- '0' & A(7 downto 1)    || 00 1011 ||---- ||---- || 00 000 1011 00 || ---- || ---- || PC_out+1   
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|-
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| 13|| RRC || A <-- C & A(7 downto 1) ,C<--  A(0)  || 00 1100 ||---- ||---- || 00 000 1110 XX || ---- || ---- || PC_out+1   
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|-
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| 14|| RLC || A <-- A(6 downto 0) & C ,C<--  A(7) || 00 1101 ||---- ||---- || 00 000 1111 XX || ---- || ---- || PC_out+1 
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|-
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| 15|| And_A_B || A <-- A and R(operand)        || 00 1110 ||---- || operand(2 downto 0) || 00 000 0100 10 || ----    || ---- || PC_out+1 
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|-
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| 16|| OR_A_B || A <-- A or R(operand)          || 00 1111 ||---- || operand(2 downto 0) || 00 000 0101 10 || ----    || ---- || PC_out+1 
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|-
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| 17|| XOR_A_B || A <-- A xor R(operand)        || 01 0000 ||---- || operand(2 downto 0) || 00 000 0110 10 || ----    || ---- || PC_out+1 
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|-
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| 18|| FlipA || A <-- not (A)                    || 01 0001  ||---- ||---- || 00 000 1100 00 || ----    || ---- || PC_out+1 
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|-
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| 19|| NegA || A <-- not(A) + 1                  || 01 0010  ||---- ||---- || 00 000 1001 00 || ---- || ---- || PC_out+1 
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|-
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| 20|| Jmp || PC <-- Operand                    || 01 0011  ||---- ||---- || 00 000 0010 XX || ---- || ---- || Operand 
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|-
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| 21|| JmpZ || if Z = 1: PC <-- Operand || 01 0100  ||---- ||---- || 00 000 0010 XX || ---- || ---- || if Z=1 then Operand else PC_out+1
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|-
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| 22|| JmpOV || if OV = 1: PC <-- Operand || 01 0101  ||---- ||---- || 00 000 0010 XX || ---- || ---- || if OV=1 then Operand else PC_out+1
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|-
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| 23|| JmpC || if C = 1: PC <-- Operand || 01 0110  ||---- ||---- || 00 000 0010 XX || ---- || ---- || if C=1 then Operand else PC_out+1
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|-
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| 24|| Jmp_rel || PC <-- PC + Operand  || 01 0111  ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC <-- PC + Operand 
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|-
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| 25|| JMPEQ || if EQ = 1: PC <-- Operand || 01 1000  ||---- ||---- || 00 000 0010 XX || ---- || ---- || if EQ=1 then Operand else PC_out+1
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|-
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| 26|| ClearZ || Z <--- 0 || 01 1001  ||---- ||---- || 00 001 0010 XX || ---- || ---- ||  PC_out+1 
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|-
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| 27|| ClearOV || OV <--- 0 || 01 1010  ||---- ||---- || 00 010 0010 XX || ---- || ---- || PC_out+1   
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|-
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| 28|| ClearC || C <--- 0 || 01 1011  ||---- ||---- || 00 100 0010 XX || ---- || ---- || PC_out+1   
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|-
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| 29|| ClearACC    || ACC <-- 0          || 01 1100  ||---- ||---- || 00 000 1101 XX || ---- || ---- || PC_out+1 
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|-
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| 30|| LoadPC      || PC <---- A          || 01 1101  ||---- ||---- || 00 000 0010 XX || ---- || ---- || A 
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|-
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| 31|| SavePC      || A <---- PC          || 01 1110  ||---- ||---- || 00 000 0011 01 || PC || ---- || PC_out+1   
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|-
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| 32|| Load_A_Mem  || A <-- Mem[Operand]  || 01 1111  ||---- ||---- || 00 000 0011 00 || ---- || Operand || PC_out+1   
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|-
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| 33|| Store_A_Mem || Mem[Operand] <-- A  || 10 0000  ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1   
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|-
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| 34|| Load_R0_Dir || R0 <-- Operand      || 10 0001  || 00000001 ||---- || 01 000 0010 XX || Operand || ---- || PC_out+1   
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|-
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| 35||Load_R0_Mem  || R0 <-- Mem[Operand] || 10 0010  || 00000001 ||---- || 11 000 0010 XX || ---- || Operand || PC_out+1   
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|-
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| 36||Load_A_R    || A <-- R(operand)    || 10 0011 ||---- || operand(2 downto 0) || 00 000 0011 XX || ---- || ---- || PC_out+1   
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|-
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| 37||Load_R_A    || R(operand) <-- A    || 10 0100 || operand(7 downto 0) ||---- || 10 000 0010 XX || ---- || ---- || PC_out+1   
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|-
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| 38||Load_Ind_A  || A <-- M[A]          || 10 0101 ||---- ||---- || 00 000 0011 00 || ---- || A || PC_out+1   
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|-
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| 39|| PUSH || Mem [0 + SP] <--- A,SP <--- SP + 1 || 11 1100 ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1 
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|-
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| 40|| POP || A <--- Mem [0 + SP - 1],SP <--- SP - 1 || 11 1101 ||---- ||---- || 00 000 0011 00 || ---- || SP - 1 || PC_out+1 
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|-
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| 41|| NOP || NOP || 11 1110 ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC_out+1 
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|-
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| 42|| HALT || HALT || 11 1111 ||---- ||---- || 00 000 0010 XX || ---- || ---- || PC 
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|}
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==== Implementation of complex instructions====
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the following instructions can be also implemented with the ones in IS:
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* Call "function_name":
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PUSH
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SavePC
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Push
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Jmp "function address"
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POP 
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* Return:
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POP
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Add_A_Dir 4
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LoadPC
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* IndJMP "MemAddress":
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PUSH
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Load_A_Mem "MemAddress"
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LoadPC
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Note: its important to POP back the ACC value on the jump destination.
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* JmpR:
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PUSH
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Load_A_R "----"
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LoadPC
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Note: its important to POP back the ACC value on the jump destination.
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* JmpIndx:
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PUSH
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Load_Ind_A
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LoadPC
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Note: its important to POP back the ACC value on the jump destination.
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=== DataPath unit===
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[[File:DPU.png|350px|thumb|right|alt= text| Fig 4: DPU block diagram]]
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Datapath unit includes an Arithmetic Logical Unit (ALU), one Accumulator(ACC) and one general purpose register(Register B) and 2 multiplexers along with the flags (see Fig. 3). 
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The DPU command is formed as following:
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[[File:DPUCommand.png|400px]]
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====ALU Multiplexer====
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The ALU multiplexer chooses the inputs according to the table 2.
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{| class="wikitable floatright"
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|-
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|+ Table 2: ALU Mux
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! !! command !! output
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|-
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| 1 ||  00  || MemDATA
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|-
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| 2 ||  01  || ControlDATa
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|-
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| 3 ||  10  || B
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|-
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| 4 ||  11  || 1
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|-
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|}
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====Register File====
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[[File:RegisterSet.png|250px|thumb|right|alt= text| Fig 5: Register File Schematic]]
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The schematic of register file is show in figure 5. The Input multiplexer chooses the inputs according to the table 3.
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Each register has a small 2 to 1 multiplexer that chooses whether the input is coming from the outside or keeping the old value.
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The control for 2 to 1 multiplexers is one hot code that comes from the first 8 bits of operand (this will be used only during
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writing to Reg-file).
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The control signals for output registers are binary encoded and are the first three bits of the operand (in case of any operation
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involving a register).
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{| class="wikitable floatright"
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|-
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|+ Table 3: Register file input Mux
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! !! command !! output
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|-
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| 1 ||  00  || (others=>'0')
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|-
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| 2 ||  01  || ControlDATA
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|-
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| 3 ||  10  || ALUResult
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|-
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| 4 ||  11  || MemDATA
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|-
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|}
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====ALU====
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The ALU covers the following operations:
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{| class="wikitable"
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|-
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|+ Table 4: ALU commands
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! !! Command !! Operation !! Description
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|-
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| 1 ||  0000  || A + B || Addition
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|-
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| 2 ||  0001  || A - B || subtraction
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|-
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| 3 ||  0010  || A || Bypass A
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|-
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| 4 ||  0011  || B || Bypass B
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|-
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| 5 ||  0100  || A AND B || bitwise And
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|-
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| 6 ||  0101  || A OR B || bitwise OR
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|-
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| 7 ||  0110  || A XOR B || bitwise XOR
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|-
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| 8 ||  0111  || '0' & A(BITWIDTH-1 DOWNTO 1) || Logical Shift Right
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|-
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| 9 ||  1000  || A(BITWIDTH-2 DOWNTO 0) & '0' || Logical Shift Left
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|-
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| 10 ||  1001  || NOT(A) + 1 || Negation
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|-
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| 11 ||  1010  || A(BITWIDTH-1) & A(BITWIDTH-1 DOWNTO 1) || Arithmetic Shift Right
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|-
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| 12 ||  1011  || A(BITWIDTH-1) & A(BITWIDTH-3 downto 0)& A(0) || Arithmetic Shift Left
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|-
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| 13 ||  1100  || NOT(A) || Flip
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|-
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| 14 ||  1101  || 0 || Clear A
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|-
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| 15 ||  1110  || Cflag  & A(BITWIDTH-1 downto 1) || Rotate Right Through Carry
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|-
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| 16 ||  1111  || A(BITWIDTH-2 downto 0)& Cflag || Rotate Left Through Carry
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|}
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For addition/subtraction a ripple carry model is made out of chain of full adders.
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====Flags====
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{| class="wikitable floatright"
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|-
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|+ Table 5: DPU Flag
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! !! command !! FlagToClear
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|-
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| 1 ||  001  || Clear Z
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|-
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| 2 ||  010  || Clear OV
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|-
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| 3 ||  100  || Clear C
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|-
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|}
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In DPU has the following flags:
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* '''Zero Flag (Z)''': will be set if the result of the operation is zero
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* '''Overflow Flag (OV)''': will be set if an overflow happens in signed operations (as an example if we have 8 bit addition of 82+91 the answer we expect is 173 but the result would be interpreted as -45). Overflow flag can be realized in the following way:
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* '''Carry Flag (C)''': will be set if the unsigned addition or subtraction results in a carry.
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* '''Equal Flag (EQ)''': will be set if ACC value is equal to the operand
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To clear flags,the SetFlag commands are used in DPU command (see table 5).
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=== Instruction Memory (ROM) ===
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Instruction memory is a read only memory that user will fill in the beginning.
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=== Data Memory ===
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[[File:DataMem.png|300px|thumb|right|alt= text| Fig 6: Data Memory block diagram]]
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Data memory is made out of blocks of 1024 registers. If user wants bigger size memory, it would be necessary to add more blocks.
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Writing into data memory takes one clock cycle but reading from it can be done instantly(or in relatively shorter time). So we can assume that if we issue address in one clock cycle, we can get the data in the same clock cycle.
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There is a stack is at the top of data memory and its size is not restricted. Behavioural VHDL description of one instance of data memory is shown in the code below.
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−
 
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=== Control unit===
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[[File:ControllerFSM.png|300px|thumb|right|alt= text| Fig 7: Control unit FSM]]
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+
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Control unit has four states:
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* '''Fetch''': fetches the instructions from instruction memory and loads it in Instruction Register (IR). DPU is IDLE. No Read from data memory.
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* '''Decode''': decodes the information in IR. DPU is IDLE. No Read from data memory.
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* '''Execute''': if execution on DPU is needed the proper control signals would be provided, otherwise DPU will stay IDLE. Read from data memory performed if needed.
+
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* '''WriteBack''': in case there is a need to write a data into memory it will happen in this stage. All changes in Program Counter(PC) is happening here so all conditional and unconditional branching would be decided in this state. in case the instruction is HALT the PC would be frozen.
+
−
 
+
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=== VHDL complete versions===
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* [[:File:PicoCPU_VHDL_8Bit.zip|8-bit Version]]  (17 dec 2014)
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* 16-bit Version
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* 32-bit Version
+
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+
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=== Functional Testing ===
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Following machine code program has been made to test functionality of all instructions. The test program doesn’t cover all the cases but run through all the instructions.
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(at the moment not all the instructions are covered-12% missing)
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−
 
+
−
<source lang="javascript" collapse="true" first-line="1">
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−
Load_R0_Dir "00011000"
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OR_A_R  "00000000"
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IncA
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Sub_A_R "00000000"
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NOP
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JmpC "00001000"   
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NOP
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NOP
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−
RRC
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RLC
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NOP
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ClearC
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Store_A_Mem  "00010000"
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PUSH
+
−
SavePC
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−
PUSH
+
−
Jump "00010101"
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POP
+
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ShiftArithL
+
−
DecA
+
−
HALT
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−
Load_A_Mem "00010000"
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−
And_A_R "00000000"
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JmpZ "00011001"
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NOP
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−
ClearZ
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Add_A_Mem "00010000"
+
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Sub_A_Mem "00010000"
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Add_A_R "00000000" 
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Sub_A_Dir "00001100"
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FlipA
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XOR_A_R "00000000"
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NegA
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−
ShiftArithR
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−
ShiftA_L
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ShiftA_R
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ClearACC
+
−
POP
+
−
Add_A_Dir  "00000011"
+
−
LoadPC
+
−
HALT
+
−
</source>
+
−
 
+
−
=== Synthesizing and implementation on FPGA ===
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−
One of the parts of this project is to synthesize 8-bit version of CPU on an FPGA board. "Nexsys 3" board from Digilent has been chosen for implementation.
+
−
Clock source is controllable via a switch on the board. ClK would be either the 100MHz on-board oscillator or generated signal from one push button (for debugging).
+
−
The Accumulator value will be displayed on Seven-Segments and the flag values will be displayed on the LEDs.
+
−
 
+
−
You need the following files along the CPU VHDL files for synthesis on and implementation on FPGA:
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−
* Top-level Entity:  [[:File:TopLevel.vhd|TopLevel.vhd]]
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−
* Denouncing circuit: [[:File:Debouncer.vhd|Debouncer.vhd]]
+
−
* Seven-segment Decoder: [[:File:VectorToSevenSeg.vhd|SevenSegment.vhd]]
+
−
 
+
−
'''Important note''': Make sure you set the "FPGA Start-Up Clock" to "JTAG Clock".
+
−
====The User Constraint File (UCF)====
+
−
The following is the user constraints file for the project:
+
−
<source lang="javascript" collapse="true" first-line="1">
+
−
NET clk LOC = V10;
+
−
NET rst LOC = C4;
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−
NET ClkBttn LOC = D9;
+
−
NET ClockSrc LOC = T10;
+
−
 
+
−
NET FlagOutput<0> LOC = U16;
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−
NET FlagOutput<1> LOC = V16;
+
−
NET FlagOutput<2> LOC = U15;
+
−
NET FlagOutput<3> LOC = V15;
+
−
 
+
−
NET SevenSeg<6> LOC = T17;
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−
NET SevenSeg<5> LOC = T18;
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−
NET SevenSeg<4> LOC = U17;
+
−
NET SevenSeg<3> LOC = U18;
+
−
NET SevenSeg<2> LOC = M14;
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NET SevenSeg<1> LOC = N14;
+
−
NET SevenSeg<0> LOC = L14;
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−
 
+
−
NET AN<3> LOC = P17;
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NET AN<2> LOC = P18;
+
−
NET AN<1> LOC = N15;
+
−
NET AN<0> LOC = N16;
+
−
</source>
+
−
 
+
−
==Graphics Card Design==
+
−
 
+
−
===VGA Controller===
+
−
A simple VGA controller has been designed and synthesised on Nexsys 3 board for the PicoCPU. Controller reads a frame from a video memory and displays it on the monitor. The memory is shared between VGA controller and the graphics processor (coming soon). The user constraint file (UCF) for the vga controller can be found here:
+
−
<source lang="javascript" collapse="true" first-line="1">
+
−
missing ucf file
+
−
</source>
+
−
 
+
−
=== Graphics processor===
+
−
 
+
−
== Future plans ==
+
−
The following are the future plans for CPU:
+
−
+
−
* implement barrel shift on acc
+
−
* Adding I/O
+
−
** first try would be Input and Output registers
+
−
** wishbone bus maybe?
+
−
* Adding interrupts + super user mode (motorla has it MC68K)?
+
−
* Pipelining
+
−
* Branch prediction
+
−
* UART implementation
+
−
* implementation of Timers/Counters and peripherals
+
−
* Direct Memory Access (DMA)
+
−
* Memory management unit (MMU)
+
−
 
+
−
= Assembler =
+
−
 
+
−
==Python Assembly translator==
+
−
A simple assembly translator was designed to make debugging process faster. Here you can see 32 bit version of the code:
+
−
+
−
<source lang="javascript" collapse="true" first-line="1">
+
−
import re
+
−
InstructionOpCode = {
+
−
 
+
−
                'Add_A_B': "000000",
+
−
                'Add_A_Mem': "000001",
+
−
                'Add_A_Dir': "000010",
+
−
                'Sub_A_B': "000011",
+
−
                'Sub_A_Mem': "000100",
+
−
                'Sub_A_Dir': "000101",
+
−
 
+
−
                'IncA': "000110",
+
−
                'DecA': "000111",
+
−
 
+
−
                'ShiftArithR': "001000",
+
−
                'ShiftArithL': "001001",
+
−
                'ShiftA_R': "001010",
+
−
                'ShiftA_L': "001011",
+
−
                'RRC':   "001100",
+
−
                'RLC': "001101",
+
−
 
+
−
                'And_A_B': "001110",
+
−
                'OR_A_B': "001111",
+
−
                'XOR_A_B': "010000",
+
−
                'FlipA': "010001",
+
−
                'NegA': "010010 ",
+
−
 
+
−
                'Jump': "010011",
+
−
                'JmpZ': "010100",
+
−
                'JmpOV': "010101",
+
−
                'JmpC': "010110",
+
−
                'Jmp_rel': "010111",
+
−
                'JMPEQ': "011000",
+
−
 
+
−
                'ClearZ': "011001",
+
−
                'ClearOV': "011010 ",
+
−
                'ClearC': "011011",
+
−
                'ClearACC': "011100",
+
−
 
+
−
                'LoadPC': "011101",
+
−
                'SavePC': "011110",
+
−
 
+
−
                'Load_A_Mem': "011111",
+
−
                'Store_A_Mem': "100000",
+
−
                'Load_B_Dir': "100001",
+
−
                'Load_B_Mem': "100010",
+
−
 
+
−
                'Load_A_B': "100011",
+
−
                'Load_B_A': "100100",
+
−
                'Load_Ind_A ': "100101",
+
−
 
+
−
                'PUSH': "111100",
+
−
                'POP': "111101",
+
−
                'NOP': "111110",
+
−
                'HALT': "111111",
+
−
 
+
−
}
+
−
AssemblyFile = open('Assembly.txt', 'r+')
+
−
MachineCodeFile = open('MachineCode.txt', 'w')
+
−
counter=0
+
−
for line in AssemblyFile:
+
−
 
+
−
    for key in InstructionOpCode:
+
−
        if key in line:
+
−
            operand= "00000000"
+
−
            if "Mem" in line:
+
−
                operand = re.findall(r'\d+',line)[0]
+
−
            elif "Jmp" in line:
+
−
                operand = re.findall(r'\d+',line)[0]
+
−
            elif "Dir" in line:
+
−
                operand = re.findall(r'\d+',line)[0]
+
−
            operand = "00000000"+"00000000"+"00000000"+ operand
+
−
            MachineCodeFile.write(str(counter)+ " =>  "+ "\"00"+InstructionOpCode[key]+operand+'\",'+'\n')
+
−
            counter +=1
+
−
 
+
−
MachineCodeFile.close()
+
−
AssemblyFile.close()
+
−
</source>
+
−
 
+
−
==Java Assembler==
+
−
This Assembler is wrote by Karl Janson as a project during system modelling course. You can find the information about how to use it in the [[PicoAssembler user manual and syntax reference|User Manual]].
+
−
 
+
−
===Downloads===
+
−
* Executable File:
+
−
* The Assembler code: [[:File:picoAssembler.zip]]
+
−
* Assembler Instructions File: [[:File:intructions.txt]]
+
−
 
+
−
Note: Codes and User Manual for the assembler are placed in the Public Domain with the authorization of its author, Karl Janson.
+
−
 
+
−
= Compiler =
+

Latest revision as of 15:32, 24 November 2015

CPU project is one of the projects designed in department of computer engineering at TTU as a lab project to provide students with some tools for studying CPU architecture.

CPU implementations

Currently, there are two different CPU implementations:

  • picoCPU: a very simple, simulation oriented CPU written in VHDL.
  • A More Advanced CPU: a synthesizable CPU written in VHDL. It has also some more advanced features compared to the picoCPU, like stack, pipeline, etc.

picoAssembler

PicoAssembler is a simple, reconfigurable assembler that can be used together with the processors described above More info on this can be found on the PicoAssembler user manual and syntax reference page.

Retrieved from "https://strudel.pld.ttu.ee/wiki/e/index.php?title=CPUProject&oldid=2007"