IAX0600 Digital Systems Design (LABS)

To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of written reports. 60 points are awarded for passing all the labs and 40 points are awarded for passing the final exam.

Lecturer:

associate professor Alexander Sudnitson

Lab Assistant:

research scientist Dmitri Mihhailov

Lab Syllabus :

[PDF]

Important !!! :

changes in the lab order due to national emergency situation [PDF]

Reports and source files:

dmitri.mihhailov@taltech.ee (cc: aleksander.sudnitson@taltech.ee)
[MAILTO]

Results:

[LINK]

Useful Links and Materials:
  1. Basys 3 FPGA Board Reference Manual [PDF]
  2. Basys 3 FPGA Board Master XDC File [XDC]
  3. Installing Vivado and Digilent Board Files [LINK]
  4. Getting Started with Vivado [LINK]
  5. Getting Started with the Vivado IP Integrator [LINK]
  6. Xilinx Vivado IDE User Guide [PDF]

Requirements and Deadlines:

Deadline for passing the lab course is 14.05.2021

All Labs give 60 points to the final grade

No points are awarded if the lab is not passed within deadline (as specified above and in Lab Syllabus)

Additional 5 points (Bonus 1) are awarded if labs 1-3 are passed until 30.03.2021

Additional 5 points (Bonus 2) are awarded if labs 1-5 are passed until 14.05.2021

Tasks:
  1. (02.02.2021) Labs Overview [PPT]
  2. (03.02.2021) Basic Vivado Tutorial : Part 1 [PPT]
  3. (10.02.2021) Basic Vivado Tutorial : Part 2 [PPT]
  4. (17.02.2021) Lab 1 : Logic Gates [PDF] Appendix [PDF]
  5. (03.03.2021) Lab 2 : Combinational Logic [PDF] Appendix [PDF]
  6. (17.03.2021) Lab 3 : Structural Design [PDF]
  7. (31.03.2021) Lab 4 : Sequential Logic [PDF] Appendix [PDF]
  8. (21.04.2021) Lab 5 : Creeping Line Project [PDF]