Selected Publications

 

  1. R. Ubar, A. Jutman, "Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns," Proc. of 6th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES'99), Krakow, Poland, June 17-19, 1999, pp. 437-442.
  2. A. Jutman, R. Ubar, "Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model," Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.
  3. R. Ubar, A. Jutman, Z. Peng, "Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs", Proc. of IEEE Conference NORCHIP'2000, Turku, Finland, November 6-7, 2000, pp. 254-261.
  4. A. Jutman, R. Ubar, Z. Peng, "Timing Simulation of Digital Circuits with Binary Decision Diagrams," Proc. of Design, Automation & Test in Europe Conference & Exhibition (DATE'01), Munchen, Germany, March 13-16, 2001, pp. 460-466.
  5. J. Raik, A. Jutman, R. Ubar, "Fast Static Compaction of Test Sequences Using Implications and Greedy Search" Proc. of IEEE European Test Workshop (ETW'01), Stockholm, Sweden, May 29 - June 1, 2001, pp. 207-209.
  6. A. Jutman, R. Ubar, "Laboratory Training for Teaching Design and Test of Digital Circuits," in Proc 8th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'01), Zakopane, Poland, June 21-23, 2001, pp. 521-524.
  7. A. Jutman, R. Ubar, "Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits," Proc. of the Estonian Academy of Sciences, Engineering, Vol. 7/4, 2001, pp 269-288.
  8. R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke, "Internet-Based Software for Teaching Test of Digital Circuits," in Proc. 4th European Workshop on Microelectronics Education (EWME'02). Parador de Baiona, Spain, May 23-24, 2002, pp. 317-320.
  9. J. Raik, A. Jutman, R. Ubar, "Fast and Exact Static Compaction of Sequential Circuit Tests Based on Branch-and-Bound Techniques," in Informal Digest of 7th IEEE European Test Workshop (ETW'02), Corfu, Greece, May 26-29, 2002, pp. 19-20.
  10. A. Jutman, J. Raik, R. Ubar, "SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms," in Informal Digest of 7th IEEE European Test Workshop (ETW'02), Corfu, Greece, May 26-29, 2002, pp. 345-346.
  11. S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, "Web-based training system for teaching basics of RT-level Digital Design, Test, and Design for Test," in Proc. of 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'02), Wroclaw, Poland, June 20-22, 2002, pp. 699-704.
  12. J. Raik, A. Jutman, R. Ubar, "Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods" in Proc. of 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS'02), Dubrovnik, Croatia, Sept. 15-18, 2002, Vol. 2, pp. 445-448.
  13. A. Jutman, J. Raik, R. Ubar, "SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test," in Proc. of 5th International Workshop on Boolean Problems (IWSBP'02), Freiberg, Germany, Sept. 19-20, 2002, pp. 157-166.
  14. S. Devadze, A. Jutman, A. Sudnitson, R. Ubar, H-D. Wuttke, "Teaching Digital RT-Level Self-Test using a Java Applet," in Proc. 20th IEEE Conference NORCHIP'2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.
  15. A. Jutman, A. Sudnitson, R. Ubar, "Web-based Applet for Teaching Boundary Scan Standard IEEE 1149.1" in Proc. of 10th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'03), Lodz, Poland, June 26-28, 2003, pp. 584-589.
  16. A. Jutman, A. Sudnitson, R. Ubar, H.-D.Wuttke "Java Applets Support for an Asynchronous-Mode Learning of Digital Design and Test," in Proc. of 4th International Conference on Information Technology Based Higher Education and Training (ITHET'03), Marrakech, Morocco, July 7-9, 2003, pp. 397-401.
  17. A. Jutman, "On SSBDD Model Size and Complexity", in Proc. of 4th Electronic Circuits and Systems Conference (ECS'03), Bratislava, Slovakia, September 11-12, 2003, pp. 17-22.
  18. M.Aarna, E.Ivask, A.Jutman, E.Orasson, J.Raik, R.Ubar, V.Vislogubov, H.-D.Wuttke, "Turbo Tester - Diagnostic Package for Research and Training", in Scientific-Technical Journal "Radioelectronics & Informatics". KNURE. Vol. 3(24), 2003, pp.69-73.
  19. A. Jutman, R. Ubar, H.-D. Wuttke, “Overview of E-Learning Environment for Web-Based Study of Testing and Diagnostics of Digital Systems”, in Proc. of 5th European Workshop on Microelectronics Education (EWME’04), Lausanne, Switzerland, April 15-16, 2004, pp. 173-176.
  20. A. Jutman, “Shift Register Based TPG for At-Speed Interconnect BIST”, in Proc. of 24th International Conference on Microelectronics (MIEL’04), Nis, Serbia and Montenegro, May 16-19, 2004, pp. 751-754.
  21. A. Jutman, “At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults”, in Formal Proc. of 9th European Test Symposium (ETS’04), Corsica, France, May 23-26, 2004.
  22. A. Jutman, A Sudnitson, R. Ubar, H.-D. Wuttke, “E-Learning Environment in the Area of Digital Microelectronics”, in Proc. of Int. Conf. on Information Technology Based Higher Education and Training (ITHET’04), Istanbul, Turkey, May 31 – June 2, 2004, pp. 278-283.
  23. R. Ubar, T. Vassiljeva, J. Raik, A. Jutman, M. Tombak, A. Peder, “Optimization of Structurally Synthesized BDDs”, in Proc of 4th IASTED Int. Conf. on Modeling, Simulation, and Optimization, Kauai, Hawaii, USA, August 17-19, 2004, pp. 234-240.
  24. A. Jutman A. Peder J. Raik M. Tombak R. Ubar “Structurally synthesized binary decision diagrams,” in Proc. of 6th International Workshop on Boolean Problems (IWSBP’04), Freiberg, Germany, Sept. 23-24, 2004.